Канал: VLSI_Learn's_Explore

Lec 24 MOSFET Circuit Design Part1

Lec 24 MOSFET Circuit Design Part1

Lec 25 Circuit Design Part 2

Lec 25 Circuit Design Part 2

Lec 26 Alternative CMOS Circuit Designs

Lec 26 Alternative CMOS Circuit Designs

Lec 27 Combinational Circuits using MOSFET's Structured Design

Lec 27 Combinational Circuits using MOSFET's Structured Design

Lec 29 Switch level logic Implementation

Lec 29 Switch level logic Implementation

Lec 28 MOSFET Functional Blocks

Lec 28 MOSFET Functional Blocks

Chaitanya Kommu's Personal Meeting Room

Chaitanya Kommu's Personal Meeting Room

Chaitanya Kommu's Personal Meeting Room

Chaitanya Kommu's Personal Meeting Room

Session on Introduction to VLSI Design created by Kommu Chaitanya

Session on Introduction to VLSI Design created by Kommu Chaitanya

Chaitanya Kommu's Personal Meeting Room

Chaitanya Kommu's Personal Meeting Room

Session on Introduction to VLSI Design created by Kommu Chaitanya

Session on Introduction to VLSI Design created by Kommu Chaitanya

Session on Introduction to VLSI Design created by Kommu Chaitanya

Session on Introduction to VLSI Design created by Kommu Chaitanya

Session on Introduction to VLSI Design created by Kommu Chaitanya

Session on Introduction to VLSI Design created by Kommu Chaitanya

Session on Introduction to VLSI Design Laboratory created by Kommu Chaitanya

Session on Introduction to VLSI Design Laboratory created by Kommu Chaitanya

Session on Introduction to VLSI Design Laboratory created by Kommu Chaitanya

Session on Introduction to VLSI Design Laboratory created by Kommu Chaitanya

Session on Introduction to VLSI Design created by Kommu Chaitanya

Session on Introduction to VLSI Design created by Kommu Chaitanya

Chaitanya Kommu's Personal Meeting Room

Chaitanya Kommu's Personal Meeting Room

Chaitanya Kommu's Personal Meeting Room

Chaitanya Kommu's Personal Meeting Room

Session on Introduction to VLSI Design created by Kommu Chaitanya

Session on Introduction to VLSI Design created by Kommu Chaitanya

Session on Shift Registers created by Kommu Chaitanya

Session on Shift Registers created by Kommu Chaitanya

Session on Introduction to VLSI Design Laboratory created by Kommu Chaitanya

Session on Introduction to VLSI Design Laboratory created by Kommu Chaitanya

FDLC_Lec _11: Hamming Code

FDLC_Lec _11: Hamming Code

FDLC_Lec_10: Binary Codes

FDLC_Lec_10: Binary Codes

FDLC_Lec_9: Arithmetic's with complements

FDLC_Lec_9: Arithmetic's with complements

FDLC_Lec_8: Complements

FDLC_Lec_8: Complements

FDLC_Lec_7: Arithmetic's

FDLC_Lec_7: Arithmetic's

Lec_28 MOSFET Functional Blocks

Lec_28 MOSFET Functional Blocks

FDLC_Lec 6: Binary Number conversion

FDLC_Lec 6: Binary Number conversion

FDLC_Lec_5 Binary Number System

FDLC_Lec_5 Binary Number System

FDLC_Lec_4 Number conversion part 2

FDLC_Lec_4 Number conversion part 2

Lec_23 Area Capacitance

Lec_23 Area Capacitance

Lec_22 Sheet Resistance

Lec_22 Sheet Resistance

FDLC_Lec_3: Number conversion

FDLC_Lec_3: Number conversion

Lec_21 CMOS NAND gate layout and Sheet Resistance

Lec_21 CMOS NAND gate layout and Sheet Resistance

FDLC_Lec 2: Number Systems

FDLC_Lec 2: Number Systems

FDLC_Lec 1: Introduction to Digital Systems

FDLC_Lec 1: Introduction to Digital Systems

Lec_20: nMOS and CMOS Layout Diagrams

Lec_20: nMOS and CMOS Layout Diagrams

Lec_19 Lambda based Design Rules

Lec_19 Lambda based Design Rules

Lec_18 MOS Layers and Stick Diagrams

Lec_18 MOS Layers and Stick Diagrams

Lec 17 CMOS Latchup

Lec 17 CMOS Latchup

Lec_16 CMOS Inverter Switching Threshold

Lec_16 CMOS Inverter Switching Threshold

Lec_15 CMOS Inverter VTC

Lec_15 CMOS Inverter VTC

Lec_14 Pullup Pulldown Ratio, Pass transistor and Enhancement nMOS inverter.

Lec_14 Pullup Pulldown Ratio, Pass transistor and Enhancement nMOS inverter.

Lec_13 nMOS Invereter with Depletion Load

Lec_13 nMOS Invereter with Depletion Load

Lec_12 nMOS inverter with Resistive Load

Lec_12 nMOS inverter with Resistive Load

Lab_4_Part4_Decoder_2X4 testbench

Lab_4_Part4_Decoder_2X4 testbench

Lab_4_part3_Dataflow 2x4 Decoder

Lab_4_part3_Dataflow 2x4 Decoder

Lab_4_Part2_Gatelevel 2x4 Decoder

Lab_4_Part2_Gatelevel 2x4 Decoder

Lab_3_Gatelevel modeling of Full adder

Lab_3_Gatelevel modeling of Full adder

LAB_4_Part1 Dataflow Modeling of Full Adder

LAB_4_Part1 Dataflow Modeling of Full Adder

LAB_3 Gatelevel modeling of Full adder

LAB_3 Gatelevel modeling of Full adder

Lec_4 MOSFET Region of operations and Figure of Merit

Lec_4 MOSFET Region of operations and Figure of Merit

Lec_11 Transconductance gm

Lec_11 Transconductance gm

Lec_10 Channel charge and Current Equation

Lec_10 Channel charge and Current Equation

NAND post layout

NAND post layout

Inverter Post-layout simulation Using NCSU Free PDK 45nm

Inverter Post-layout simulation Using NCSU Free PDK 45nm

Inverter Tanner EDA simulation using NCSU Free PDK 45nm

Inverter Tanner EDA simulation using NCSU Free PDK 45nm

Tanner setup for NCSU Free PDK 45nm

Tanner setup for NCSU Free PDK 45nm

Lec_9 Electrical Characteristics of nMOS Transistor

Lec_9 Electrical Characteristics of nMOS Transistor

Lec_8 Twin Tub Process

Lec_8 Twin Tub Process

Lec_7 n-WELL CMOS Fabrication part 2

Lec_7 n-WELL CMOS Fabrication part 2

LEC_6 n-WELL CMOS Fabrication Part_1

LEC_6 n-WELL CMOS Fabrication Part_1

VLSI LAB1 FPGA Design flow

VLSI LAB1 FPGA Design flow

VLSI LAB2 Introduction to Verilog HDL programming

VLSI LAB2 Introduction to Verilog HDL programming

LEC_5 nMOS Fabrication

LEC_5 nMOS Fabrication

LEC_4 MOS FET Operation

LEC_4 MOS FET Operation

LEC_3 MOS Transistor Construction

LEC_3 MOS Transistor Construction

Lec_2: Introduction to IC technologies

Lec_2: Introduction to IC technologies

Lec_1: introduction to course

Lec_1: introduction to course

Gate_level_modeling for Full adder

Gate_level_modeling for Full adder

FPGA Design Part4

FPGA Design Part4

FPGA Design Part3

FPGA Design Part3

FPGA Design Part2

FPGA Design Part2

FPGA Design part1

FPGA Design part1

SM Charts Part5

SM Charts Part5

SM Charts Part4

SM Charts Part4

SM Charts Part3

SM Charts Part3

SM Chart Part2

SM Chart Part2

SM Charts Part1

SM Charts Part1

Behavioral Modeling part5

Behavioral Modeling part5

Behavioral Modeling part4

Behavioral Modeling part4

Behavioral Modeling Part3

Behavioral Modeling Part3

Behavioral Modeling part2

Behavioral Modeling part2

Behavioral Modeling part1

Behavioral Modeling part1

Switch level modeling part2

Switch level modeling part2

Switch level modeling part1

Switch level modeling part1

Verilog Operators Part2

Verilog Operators Part2

Verilog operators part1

Verilog operators part1

Dataflow Modeling

Dataflow Modeling

Verilog Strengths

Verilog Strengths

Structural modeling part3 ALU

Structural modeling part3 ALU

Structural modeling part2

Structural modeling part2

Gate Delays

Gate Delays

Structural modeling Part1

Structural modeling Part1

Gatelevel modeling part5

Gatelevel modeling part5

Gatelevel modeling part4

Gatelevel modeling part4

Gatelevel modeling part3

Gatelevel modeling part3

Gatelevel modeling part2

Gatelevel modeling part2

Gate Level Modeling PART1

Gate Level Modeling PART1

FPGA Flow Xilinx Vivado

FPGA Flow Xilinx Vivado

Lexical Tokens part2

Lexical Tokens part2

Lexical Tokens part1

Lexical Tokens part1

Modeling Styles Testbench

Modeling Styles Testbench

Modeling styles in Verilog HDL_Part2

Modeling styles in Verilog HDL_Part2

Modeling styles in Verilog HDL_Part1

Modeling styles in Verilog HDL_Part1

tinkerpad

tinkerpad

Modelsim Installation

Modelsim Installation

Introduction to Digital Design with Verilog HDL

Introduction to Digital Design with Verilog HDL