Канал: VLSI EXPERT (vlsi EG)

Overview of Physical Design (In Tamil)

Overview of Physical Design (In Tamil)

Webinar - Timing Constraints - End to End

Webinar - Timing Constraints - End to End

Placement oriented VLSI Training program

Placement oriented VLSI Training program

Testimony Nitin - Sharing Experience about VLSI EXPERT

Testimony Nitin - Sharing Experience about VLSI EXPERT

Testimony Pushkar Naniwal

Testimony Pushkar Naniwal

L4S2 - DC Analysis On HSpice

L4S2 - DC Analysis On HSpice

Testimony Kumar Gaurav - 2024 Passout

Testimony Kumar Gaurav - 2024 Passout

Testimony Uday Chand Roy - 2024 Passout

Testimony Uday Chand Roy - 2024 Passout

L3S2 - Netlist and Schematic using HSpice

L3S2 - Netlist and Schematic using HSpice

L2S2_Writing Netlist for HSpice Simulation

L2S2_Writing Netlist for HSpice Simulation

L1S2_HSPICE INTRO

L1S2_HSPICE INTRO

L8S1 - How the Shape of DIE area is defined

L8S1 - How the Shape of DIE area is defined

L7S0 - How to measure Rise & Fall time using Measure tool in Waveform Viewer from Custom Compiler

L7S0 - How to measure Rise & Fall time using Measure tool in Waveform Viewer from Custom Compiler

L7S1 - Which one is better either Metal layer 7 or 8 in a design

L7S1 - Which one is better either Metal layer 7 or 8 in a design

L6S1_Interview- CrossTalk and how it will effect the performance

L6S1_Interview- CrossTalk and how it will effect the performance

L5S1_Interview- Checks at the CTS stage

L5S1_Interview- Checks at the CTS stage

L4S1_Interview- Why Clock is Ideal in Floorplan and Placement Stage

L4S1_Interview- Why Clock is Ideal in Floorplan and Placement Stage

L3S1_Interview- Spare Cell and it's importance in Physical Design

L3S1_Interview- Spare Cell and it's importance in Physical Design

L6S0 - LVS and DRC Check using Synopsys Custom Compiler and ICV

L6S0 - LVS and DRC Check using Synopsys Custom Compiler and ICV

L5S0 - Layout of Inverter using Custom Compiler

L5S0 - Layout of Inverter using Custom Compiler

L4S0 - Voltage Transfer Characteristic of an Inverter using Symbol View in Custom Compiler

L4S0 - Voltage Transfer Characteristic of an Inverter using Symbol View in Custom Compiler

L2S1_Interview- Placement of Physical Only Cells

L2S1_Interview- Placement of Physical Only Cells

L3S0 - Create Symbol of CMOS Inverter in Custom Compiler

L3S0 - Create Symbol of CMOS Inverter in Custom Compiler

L2S0 - How to create library and multiple cell in Custom Compiler

L2S0 - How to create library and multiple cell in Custom Compiler

L1S1_Interview- APR Flow - Automatic Placement and Routing Flow

L1S1_Interview- APR Flow - Automatic Placement and Routing Flow

L1S0-Design of Schematic of CMOS Inverter using Custom Compiler

L1S0-Design of Schematic of CMOS Inverter using Custom Compiler

RC Simulation on Custom Compiler

RC Simulation on Custom Compiler

Introduction of TCL - Part 4

Introduction of TCL - Part 4

Introduction of TCL - Part 3

Introduction of TCL - Part 3

Introduction of TCL - Part 2

Introduction of TCL - Part 2

Introduction of TCL - Part 1

Introduction of TCL - Part 1

VLSI CRASH COURSE AT INR 500/- (IN PLACE OF INR 10,000/-) #thomso23 #vlsi #placement #vlsiexpert

VLSI CRASH COURSE AT INR 500/- (IN PLACE OF INR 10,000/-) #thomso23 #vlsi #placement #vlsiexpert

VLSI EXPERT at #Thomso23 IIT Roorkee

VLSI EXPERT at #Thomso23 IIT Roorkee

S1E4 - What Should You Do If "ON BENCH" (Virtual Interaction with Puneet Mittal)

S1E4 - What Should You Do If "ON BENCH" (Virtual Interaction with Puneet Mittal)

Testimony - Mahima Saxena - @synopsys

Testimony - Mahima Saxena - @synopsys

S1E3 - Work From Home Concept (Virtual Interaction with Puneet Mittal)

S1E3 - Work From Home Concept (Virtual Interaction with Puneet Mittal)

Session 2 - Concept of Word In Memory (Module 1 - Memory Decoded)

Session 2 - Concept of Word In Memory (Module 1 - Memory Decoded)

Session 1- Units of Memory (Module1 - Memory Decoded )

Session 1- Units of Memory (Module1 - Memory Decoded )

Testimony:- Amit - M.Tech. @NSIT, Delhi

Testimony:- Amit - M.Tech. @NSIT, Delhi

S1E2 - Virtual Interaction with Puneet Mittal - Why M.Tech and Is it worth?

S1E2 - Virtual Interaction with Puneet Mittal - Why M.Tech and Is it worth?

S1E1 - Virtual Interaction with Puneet Mittal - How Students Opt for Electronics Engineering

S1E1 - Virtual Interaction with Puneet Mittal - How Students Opt for Electronics Engineering

Basic Of Low Power VLSI Design - Session4 snapshot1

Basic Of Low Power VLSI Design - Session4 snapshot1

Testimony - Vishal Yadav - @Synopsys

Testimony - Vishal Yadav - @Synopsys

Testimony:- Vikas - Synopsys Placement 2022

Testimony:- Vikas - Synopsys Placement 2022

Testimony:- Jyoti Tomar - B. Tech.2020 Passout

Testimony:- Jyoti Tomar - B. Tech.2020 Passout

Static Timing Analysis - Intro Session - Part 2 - 2nd July 2023

Static Timing Analysis - Intro Session - Part 2 - 2nd July 2023

Static Timing Analysis - Intro session - Part 1 - 1 July 2023

Static Timing Analysis - Intro session - Part 1 - 1 July 2023

Physical Design Using Synopsys Tool - Intro Session - Batch 2023

Physical Design Using Synopsys Tool - Intro Session - Batch 2023

Session on "Basic Low Power concepts" By Kavita Mehta

Session on "Basic Low Power concepts" By Kavita Mehta

STA_L3e - Introduction of Transition Delay

STA_L3e - Introduction of Transition Delay

STA_L3d - Calculation of Overall Propagation Delay

STA_L3d - Calculation of Overall Propagation Delay

STA_L3c - Introduction of Propagation Delay

STA_L3c - Introduction of Propagation Delay

STA_L3b - Overview of RC Network

STA_L3b - Overview of RC Network

STA_L3a - Introduction of Delay Concepts

STA_L3a - Introduction of Delay Concepts

STA_L2i - Sequential Cell in LIB File

STA_L2i - Sequential Cell in LIB File

STA_L2h - Introduction to LIB File

STA_L2h - Introduction to LIB File

STA_L2g - Sequential Cell Timing Arc

STA_L2g - Sequential Cell Timing Arc

STA_L2f - Unateness of Complex Gates and System Timing Arc

STA_L2f - Unateness of Complex Gates and System Timing Arc

STA_L2e - Unateness of Logic Gates

STA_L2e - Unateness of Logic Gates

STA_L2d - Unateness in OR Gate

STA_L2d - Unateness in OR Gate

STA_L2c - Timing Arc and Unateness in AND Gate

STA_L2c - Timing Arc and Unateness in AND Gate

STA_L2b - Net and Cell Timing Arc

STA_L2b - Net and Cell Timing Arc

ANUDAKSH LAUNCH - An Initiative to Upskill

ANUDAKSH LAUNCH - An Initiative to Upskill

STA_L2a - Introduction of Timing Arc

STA_L2a - Introduction of Timing Arc

STA_L1j - Input Output Files of Timing Tool

STA_L1j - Input Output Files of Timing Tool

STA_L1i - Static Timing Analysis Introduction

STA_L1i - Static Timing Analysis Introduction

Future of VLSI Industry & How to Prepare for it! - SIT-NES2021

Future of VLSI Industry & How to Prepare for it! - SIT-NES2021

Gift-A-Bundle-2 - An Initiative by VLSI Expert 2021

Gift-A-Bundle-2 - An Initiative by VLSI Expert 2021

VLSI Industry Manpower Generation (Part 5)

VLSI Industry Manpower Generation (Part 5)

CMOS_S1_L4 - CMOS Technology - Different Manufacturing Defects

CMOS_S1_L4 - CMOS Technology - Different Manufacturing Defects

CMOS_S1_L3 - CMOS Technology - Width Vs Parasitic

CMOS_S1_L3 - CMOS Technology - Width Vs Parasitic

CMOS_S1_L2 - CMOS Technology - Optical Imaging System

CMOS_S1_L2 - CMOS Technology - Optical Imaging System

CMOS_S1_L1 - CMOS Technology - Fabrication Effect

CMOS_S1_L1 - CMOS Technology - Fabrication Effect

STA_S2_L1_Intro Session - Static Timing Analysis (Basic To Advance)

STA_S2_L1_Intro Session - Static Timing Analysis (Basic To Advance)

SIT - April 20, 2020: MOS Threshold voltage -I

SIT - April 20, 2020: MOS Threshold voltage -I

SIT - Apr 13, 2020 CMOS : MOS Device

SIT - Apr 13, 2020 CMOS : MOS Device

SIT - April 6, 2020: CMOS Fundamentals -- IC Devices

SIT - April 6, 2020: CMOS Fundamentals -- IC Devices

NES2020 - 3rd Day

NES2020 - 3rd Day

Walk through RTL2GDS using Skywater PDK & Open source tool - In NES2020 - (ExpertTalk - 16th Dec)

Walk through RTL2GDS using Skywater PDK & Open source tool - In NES2020 - (ExpertTalk - 16th Dec)

TinyML - By Rohit S; Future of VLSI by Atul - In NES2020 - (ExpertTalk - 16th Dec)

TinyML - By Rohit S; Future of VLSI by Atul - In NES2020 - (ExpertTalk - 16th Dec)

Transaction-Level Verilog - A Modern Approach to Integrated Circuit Design (NES-2020) Workshop -

Transaction-Level Verilog - A Modern Approach to Integrated Circuit Design (NES-2020) Workshop -

ExpertTalk - 17th Oct'20

ExpertTalk - 17th Oct'20

Modern Job Search Technique

Modern Job Search Technique

"Foundation of VLSI Design" Course By VLSI Expert (Importance of Course Content)

"Foundation of VLSI Design" Course By VLSI Expert (Importance of Course Content)

ExpertTalk - 19th Sept' 20

ExpertTalk - 19th Sept' 20

ExpertTalk - 19th Sept' 20

ExpertTalk - 19th Sept' 20

How to Build Resume for VLSI Industry

How to Build Resume for VLSI Industry

ExpertTalk - 15th Aug' 20

ExpertTalk - 15th Aug' 20

Resume Building Seminar By Exprtie

Resume Building Seminar By Exprtie

Testimony:- Sparsh Jindal - B.Tech. 2020 passout

Testimony:- Sparsh Jindal - B.Tech. 2020 passout

18 July 2020' ExpertTalk (An Initiative by VLSI Expert)

18 July 2020' ExpertTalk (An Initiative by VLSI Expert)

SIT - 27th April 2020 - CMOS Working

SIT - 27th April 2020 - CMOS Working

SIT - Standard Cell Basics - 4th May2020

SIT - Standard Cell Basics - 4th May2020

SIT - 11th May 2020 - CMOS Working

SIT - 11th May 2020 - CMOS Working

SIT - 18th May 2020 - CMOS - Inverter Characteristic

SIT - 18th May 2020 - CMOS - Inverter Characteristic

SIT - Installing CppSim - 5th May2020

SIT - Installing CppSim - 5th May2020

Logic Synthesis and STA - S1_L1 - Intro Session

Logic Synthesis and STA - S1_L1 - Intro Session

Subhra Mahapatra - Testimony - Synopsys Placement 2020

Subhra Mahapatra - Testimony - Synopsys Placement 2020

VLSI Industry Manpower Generation (Part 4)

VLSI Industry Manpower Generation (Part 4)

VLSI Industry Manpower Generation (Part 3)

VLSI Industry Manpower Generation (Part 3)

VLSI Industry Manpower Generation (Part 2)

VLSI Industry Manpower Generation (Part 2)

Physical Design - 1g - QnA Session (in Hindi)

Physical Design - 1g - QnA Session (in Hindi)

Physical Design - 1f - ICC2 - Floorplan 2 - Dataflow Lines,Register Tracing & Congestion Analysis

Physical Design - 1f - ICC2 - Floorplan 2 - Dataflow Lines,Register Tracing & Congestion Analysis

Physical Design - 1e - ICC2 - Floorplan 1 - Different Stages

Physical Design - 1e - ICC2 - Floorplan 1 - Different Stages

Physical Design - 1d - ICC2 Overview - Timing Setup

Physical Design - 1d - ICC2 Overview - Timing Setup

Physical Design - 1c - ICC2 Overview - Design Setup & NDM Libraries

Physical Design - 1c - ICC2 Overview - Design Setup & NDM Libraries

Physical Design - 1b - PnR Flow Overview - Top level Vs Block Level

Physical Design - 1b - PnR Flow Overview - Top level Vs Block Level

Physical Design - 1a - ICC2 Overview - Design planning & Task Assistance

Physical Design - 1a - ICC2 Overview - Design planning & Task Assistance

Static Timing Analysis - Course overview - 4th Jan 2020

Static Timing Analysis - Course overview - 4th Jan 2020

VLSI Industry Manpower Generation (part 1)

VLSI Industry Manpower Generation (part 1)

VLSI Expert - Student's View : Madhuparna

VLSI Expert - Student's View : Madhuparna

VLSI Expert's Candiate Review : Reskilling

VLSI Expert's Candiate Review : Reskilling

STA_L1h - STA Tool & Flow at different stages

STA_L1h - STA Tool & Flow at different stages

STA_L1g - Timing Check Overview in PD Flow

STA_L1g - Timing Check Overview in PD Flow

STA_L1f - Overview of Floorplan Aware Synthesis

STA_L1f - Overview of Floorplan Aware Synthesis

STA_L1e -Timing Optimization During Logic Synthesis

STA_L1e -Timing Optimization During Logic Synthesis

VLSI Expert Overview

VLSI Expert Overview

STA_L1d - Importance of Timing From RTL to Logic Synthesis

STA_L1d - Importance of Timing From RTL to Logic Synthesis

STA_L1c Overview of VLSI Backend Design Flow

STA_L1c Overview of VLSI Backend Design Flow

STA_L1b - Overview of VLSI Frontend Design Flow

STA_L1b - Overview of VLSI Frontend Design Flow

STA_L1a - Overview of RTL 2 GDS Flow

STA_L1a - Overview of RTL 2 GDS Flow

VLSI Expert - Student's View

VLSI Expert - Student's View

Static Timing Analysis -Addition of Buffer (Part of Online Course)

Static Timing Analysis -Addition of Buffer (Part of Online Course)

CTS_S1_L1: Clock Tree Synthesis Introduction (Part 1)

CTS_S1_L1: Clock Tree Synthesis Introduction (Part 1)

RC circuit Series (Answer of Question 2)

RC circuit Series (Answer of Question 2)

RC Circuit Series (Answer of Question 1)

RC Circuit Series (Answer of Question 1)

CLK_L10 - Fixing Large No of Hold Violation using Clock Skew (Part2)

CLK_L10 - Fixing Large No of Hold Violation using Clock Skew (Part2)

CLK_L9 - Fixing Large No of Hold Violation using Clock Skew (Part1)

CLK_L9 - Fixing Large No of Hold Violation using Clock Skew (Part1)

CLK_L8- Challange in Fixing Setup and Hold Violation using Clock Skew (Part2)

CLK_L8- Challange in Fixing Setup and Hold Violation using Clock Skew (Part2)

CLK_L7- Challange in Fixing Setup and Hold Violation Using Clock Skew (Part 1)

CLK_L7- Challange in Fixing Setup and Hold Violation Using Clock Skew (Part 1)

(Old Version) CLK_L7- Challange in Fixing Setup and Hold Violation Using Clock Skew

(Old Version) CLK_L7- Challange in Fixing Setup and Hold Violation Using Clock Skew

CLK_L6 - Clock Skew and Setup Violation

CLK_L6 - Clock Skew and Setup Violation

CLK_L5 - Clock Skew and Hold Violation

CLK_L5 - Clock Skew and Hold Violation

CLK_L4 - Importance of Clock Skew in Timing Analysis (Part 2)

CLK_L4 - Importance of Clock Skew in Timing Analysis (Part 2)

CLK_L3 -Importance of Clock Skew in Timing Analysis (Part 1)

CLK_L3 -Importance of Clock Skew in Timing Analysis (Part 1)

CLK_L2 -Clock Skew Introduction (Part 2)

CLK_L2 -Clock Skew Introduction (Part 2)

CLK_L1 - Clock Skew Introduction (Part 1 )

CLK_L1 - Clock Skew Introduction (Part 1 )