Канал: 李建模（James CM Li）

7 9 Combinational ATPG, FAN open source code(*optional)

7 9 Combinational ATPG, FAN open source code(*optional)

18 6 Advanced Topics: Power-aware ATPG

18 6 Advanced Topics: Power-aware ATPG

18 5 Advanced Topics: timing-aware ATPG

18 5 Advanced Topics: timing-aware ATPG

18 4 Advanced Topics: N-detect, cell-aware tests

18 4 Advanced Topics: N-detect, cell-aware tests

18 3 Advanced Topics: IDDQ testing

18 3 Advanced Topics: IDDQ testing

18 1 Advanced Topics: Defects

18 1 Advanced Topics: Defects

18 2 Advanced Topics: Defect-based testing, Very Low Voltage testing

18 2 Advanced Topics: Defect-based testing, Very Low Voltage testing

17 2 FunctionTest CheckExp (revised June, 2021)

17 2 FunctionTest CheckExp (revised June, 2021)

2 4 LogicSim EventDriven (new version 2021)

2 4 LogicSim EventDriven (new version 2021)

8 5 Sequential ATPG Conclusion (*optional)

8 5 Sequential ATPG Conclusion (*optional)

8 4 Sequential ATPG Simulation (*optional)

8 4 Sequential ATPG Simulation (*optional)

8 3 Sequential ATPG: Backward Time Frame Processing (*optional)

8 3 Sequential ATPG: Backward Time Frame Processing (*optional)

10 4 Diagnosis EffectCause (*optional)

10 4 Diagnosis EffectCause (*optional)

15 3 Test Compress Hardware Stimulus (updated 5/10/2020)

15 3 Test Compress Hardware Stimulus (updated 5/10/2020)

5 5 FaultSim DiffFsim(*optional)

5 5 FaultSim DiffFsim(*optional)

10 5 Diagnosis, Chain Diagnosis (*optional)

10 5 Diagnosis, Chain Diagnosis (*optional)

16 3 MemTest March

16 3 MemTest March

16 2 Memory Test - Classical algorithms

16 2 Memory Test - Classical algorithms

16 1 MemTest Intro

16 1 MemTest Intro

4 2 Dominance Fault Collapsing, DFC (*optional)

4 2 Dominance Fault Collapsing, DFC (*optional)

11 2 DFT1 ScanConcepts

11 2 DFT1 ScanConcepts

13 2 BIST1 LFSR

13 2 BIST1 LFSR

13 5 BIST1 CA

13 5 BIST1 CA

9 3 DelayTest PathTG

9 3 DelayTest PathTG

12 3 DFT2 Instruction (New version)

12 3 DFT2 Instruction (New version)

15 3 TestCompress HardwareStimulus

15 3 TestCompress HardwareStimulus

7 2 Combinational ATPG (Boolean Difference)

7 2 Combinational ATPG (Boolean Difference)

7 5 Combinational ATPG, PODEM

7 5 Combinational ATPG, PODEM

7 7 Combinational ATPG, SAT

7 7 Combinational ATPG, SAT

3 4 FaultModeling DelayFault

3 4 FaultModeling DelayFault

5 6 FaultSim Alternatives

5 6 FaultSim Alternatives

3 3 FaultModeling BridgeFault

3 3 FaultModeling BridgeFault

2 4 LogicSim EventDriven

2 4 LogicSim EventDriven

2 3 LogicSim CompliedCode

2 3 LogicSim CompliedCode

1 2 Introduction Types Of Tests

1 2 Introduction Types Of Tests

1 5 ReferenceDedication (*optional)

1 5 ReferenceDedication (*optional)

17 3 FunctionTest IOV

17 3 FunctionTest IOV

17 4 FunctionTest SV (*optional)

17 4 FunctionTest SV (*optional)

15 4 TestCompress HardwareResponse (*optional)

15 4 TestCompress HardwareResponse (*optional)

17 1 FunctionTest Intro

17 1 FunctionTest Intro

15 3 TestCompress HardwareStimulus

15 3 TestCompress HardwareStimulus

14 6 BIST2 IssuesConclude (*optional)

14 6 BIST2 IssuesConclude (*optional)

12 4 DFT2 Instruction2Conclude

12 4 DFT2 Instruction2Conclude

13 4 BIST1 LFSR polynomial

13 4 BIST1 LFSR polynomial

14 3 BIST2 Parallel ORA MISR

14 3 BIST2 Parallel ORA MISR

12 2 DFT2 JTAG Registers

12 2 DFT2 JTAG Registers

11 8 DFT1 IssueSol

11 8 DFT1 IssueSol

11 7 DFT1 ScanDesignFlow

11 7 DFT1 ScanDesignFlow

11 4 DFT1 Muxed-D Scan ATPG model (*optional)

11 4 DFT1 Muxed-D Scan ATPG model (*optional)

11 5 DFT1 ClockScan (*optional)

11 5 DFT1 ClockScan (*optional)

9 4 DelayTest PathFsim

9 4 DelayTest PathFsim

9 3 DelayTest PathTG

9 3 DelayTest PathTG

7 8 Combinational ATPG, acceleration techniques

7 8 Combinational ATPG, acceleration techniques

7 3 Combinational ATPG (Single Path Sensitization)

7 3 Combinational ATPG (Single Path Sensitization)

2 6 LogicSim Issues (* optional)

2 6 LogicSim Issues (* optional)

3 5 FaultModeling TransistorFault (* optional)

3 5 FaultModeling TransistorFault (* optional)

3 4 FaultModeling DelayFault

3 4 FaultModeling DelayFault

6 2 Testability SCOAPseq (*optional)

6 2 Testability SCOAPseq (*optional)

5 3 FaultSim Deductive

5 3 FaultSim Deductive

5 6 FaultSim Alternatives

5 6 FaultSim Alternatives

7 6 Combinational ATPG, FAN

7 6 Combinational ATPG, FAN

3 3 FaultModeling BridgeFault

3 3 FaultModeling BridgeFault

2 4 LogicSim EventDriven

2 4 LogicSim EventDriven

1 4 Introduction Test Economics

1 4 Introduction Test Economics

2 5 LogicSim Parallel

2 5 LogicSim Parallel

2 3 LogicSim CompliedCode

2 3 LogicSim CompliedCode

1 3 Introduction TestQuality

1 3 Introduction TestQuality

1 2 Introduction TypesOfTest

1 2 Introduction TypesOfTest

1 1 Introduction: What Is Testing?

1 1 Introduction: What Is Testing?

14 4 BIST2 Architecture

14 4 BIST2 Architecture

11 1 DFT1 Intro

11 1 DFT1 Intro

15 2 TestCompress SoftwareSTC

15 2 TestCompress SoftwareSTC

12 3 DFT2 JTAG Instruction (old version)

12 3 DFT2 JTAG Instruction (old version)

15 1 TestCompress Intro

15 1 TestCompress Intro

12 1 DFT2 JTAG Intro

12 1 DFT2 JTAG Intro

11 6 DFT1 LSSD

11 6 DFT1 LSSD

14 2 BIST2 SerialORA

14 2 BIST2 SerialORA

14 1 BIST2 Intro

14 1 BIST2 Intro

13 5 BIST1 CA

13 5 BIST1 CA

10 2 Diagnosis StaticCE

10 2 Diagnosis StaticCE

13 1 BIST1 Intro

13 1 BIST1 Intro

10 3 Diagnosis DynamicCE

10 3 Diagnosis DynamicCE

7 2 CombATPG BoolDiff

7 2 CombATPG BoolDiff

10 1 Diagnosis Intro

10 1 Diagnosis Intro

9 1 DelayTest Intro

9 1 DelayTest Intro

9 5 DelayTest TransitionFsimTG

9 5 DelayTest TransitionFsimTG

8 1 SeqATPG Intro

8 1 SeqATPG Intro

8 2 SeqATPG 9value

8 2 SeqATPG 9value

7 5 CombATPG PODEM

7 5 CombATPG PODEM

8 1 Sequential ATPG Introduction

8 1 Sequential ATPG Introduction

6 1 Testability Intro

6 1 Testability Intro

8 2 Sequential ATPG (9-valued)

8 2 Sequential ATPG (9-valued)

5 2 FaultSim Parallel

5 2 FaultSim Parallel

7 1 Combinational ATPG Introduction

7 1 Combinational ATPG Introduction

6 3 Testability COP

6 3 Testability COP

5 1 FaultSim Intro

5 1 FaultSim Intro

5 7 FaultSim IssueConclusion (*optional)

5 7 FaultSim IssueConclusion (*optional)

16 2 MemTest march (update 2016.9.12)

16 2 MemTest march (update 2016.9.12)

2 2 LogicSim Model

2 2 LogicSim Model

5 2 FaultSim Parallel

5 2 FaultSim Parallel

3 6 FaultModeling- FaultDetect,FaultCoverage

3 6 FaultModeling- FaultDetect,FaultCoverage

5 1 FaultSim Intro

5 1 FaultSim Intro

3 1 FaultModeling Intro

3 1 FaultModeling Intro

3 2 FaultModeling SSF

3 2 FaultModeling SSF

2 5 LogicSim Parallel

2 5 LogicSim Parallel

5 7 FaultSim IssueConclusion

5 7 FaultSim IssueConclusion

2 1 LogicSim Intro

2 1 LogicSim Intro

17 3 Testing without Fault Model - Pseudo Exhaustive Testing (PET)

17 3 Testing without Fault Model - Pseudo Exhaustive Testing (PET)

14 5 BIST2 Design Phase Shifter for LFSR TPG

14 5 BIST2 Design Phase Shifter for LFSR TPG

13 3 BIST1 - LFSR seed solving

13 3 BIST1 - LFSR seed solving

11 3 DFT1 - Test Mode Operation (SSF & Delay Test LOS/LOC)

11 3 DFT1 - Test Mode Operation (SSF & Delay Test LOS/LOC)

9 2 Delay Test - Path Sensitize

9 2 Delay Test - Path Sensitize

7 4 Combinational ATPG, D-algorithm

7 4 Combinational ATPG, D-algorithm

5 4 Concurrent Fault Simulation

5 4 Concurrent Fault Simulation

4 1 Equivalent Fault Collapsing

4 1 Equivalent Fault Collapsing