DVCon 2012: AMIQ launches "Verissimo" - a verification-centric, UVM-aware SystemVerilog linter Скачать
DVCon 2012: Justin Sprague on his award winning paper on coding for SystemVerilog performance Скачать
Meet Bob Kurshan, Cadence Fellow and Incisive Formal R&D Leader, talks about Formal Engine Tech Скачать
DAC 2011: Distinguished Engineer Mike Stellfox on UVM, the Debug Bottleneck, and System Realization Скачать
