Канал: Chill & Learn

😉 Just say. . .🎈

😉 Just say. . .🎈

About AMBA AXI 4KB BOUNDARY | What it is & How it works

About AMBA AXI 4KB BOUNDARY | What it is & How it works

Live each day to the fullest🎈

Live each day to the fullest🎈

Find your peace...🎈 | credits: peace.struggle

Find your peace...🎈 | credits: peace.struggle

🚀 #TimeFlies #LifeZoomsBy

🚀 #TimeFlies #LifeZoomsBy

Progress. . . 🎈

Progress. . . 🎈

Unearth your true joy🎈

Unearth your true joy🎈

Nothing's new. . . :)

Nothing's new. . . :)

My Friend, It'll get easier. . .

My Friend, It'll get easier. . .

Verilog Code to Swap two variables in 5 different ways

Verilog Code to Swap two variables in 5 different ways

System Verilog Constraint Qn. asked at META | lil Tricky

System Verilog Constraint Qn. asked at META | lil Tricky

How to get a job in VLSI? | #systemverilog | #shorts

How to get a job in VLSI? | #systemverilog | #shorts

Solving subscriber's Qn | To generate a payload size 10-20 & should twice the current with prev data

Solving subscriber's Qn | To generate a payload size 10-20 & should twice the current with prev data

Find out what's wrong with the given constraint code & come up with a solution

Find out what's wrong with the given constraint code & come up with a solution

SV Constraint | To generate two non-consecutive ones for 16-bit variable

SV Constraint | To generate two non-consecutive ones for 16-bit variable

Write SV constraint to generate multiples of power 2 | Follow-up Tricky logic Qn.

Write SV constraint to generate multiples of power 2 | Follow-up Tricky logic Qn.

Write SV constraint to generate 100 phone numbers where first 3 nos in each should be '852'

Write SV constraint to generate 100 phone numbers where first 3 nos in each should be '852'

Structural & Procedural Drivers {QnAs} | Asked at Truechip Solutions | Chill & Learn

Structural & Procedural Drivers {QnAs} | Asked at Truechip Solutions | Chill & Learn

FORK-JOIN scenario Questions | with Answers

FORK-JOIN scenario Questions | with Answers

Palindrome Code | in System Verilog

Palindrome Code | in System Verilog

SV Constraint | One should generate [25:50] & other should be greater than 40 | what's cons. solver?

SV Constraint | One should generate [25:50] & other should be greater than 40 | what's cons. solver?

SV Constraint | Without using inside operator generate random values for the range 34 - 43

SV Constraint | Without using inside operator generate random values for the range 34 - 43

SV Constraint | For the range 0-100 should be present 70% & 101-255 should be present 30%

SV Constraint | For the range 0-100 should be present 70% & 101-255 should be present 30%

SV Constraint | To generate odd nos. in even locations & even nos. in odd locations

SV Constraint | To generate odd nos. in even locations & even nos. in odd locations

SV Constraint | To derive odd numbers within the range of 10 to 30

SV Constraint | To derive odd numbers within the range of 10 to 30

SV Constraint | To generate unique numbers between 99 & 100

SV Constraint | To generate unique numbers between 99 & 100

SV Constraint | To generate the pattern "0102030405"

SV Constraint | To generate the pattern "0102030405"

SV Constraint | To generate random values divisible by 5

SV Constraint | To generate random values divisible by 5

UVM Phases | Commonly used phases of all time | Which UVM phase executes first?

UVM Phases | Commonly used phases of all time | Which UVM phase executes first?

Data types - Reg, wire and logic in SV || One of the most asked interview questions

Data types - Reg, wire and logic in SV || One of the most asked interview questions

What is: UVM Sequence Item? | Sequence? | Sequencer? || Basics YOU need to know

What is: UVM Sequence Item? | Sequence? | Sequencer? || Basics YOU need to know

#, @ and wait blocking statements | Co-relation between these delays

#, @ and wait blocking statements | Co-relation between these delays

begin-end vs fork-join || Is fork-join synthesizable or not? | #shorts

begin-end vs fork-join || Is fork-join synthesizable or not? | #shorts

fork...join || join_any || join_none | #shorts #systemverilog #verilog #verification #vlsi

fork...join || join_any || join_none | #shorts #systemverilog #verilog #verification #vlsi

Fork join & its types in V & SV || Overview

Fork join & its types in V & SV || Overview

Practical example for the System tasks $display & $strobe || Tamil

Practical example for the System tasks $display & $strobe || Tamil

UVM Testbench Flow | What 's UVM? | Why UVM? | Basic UVM Hierarchy YOU should know

UVM Testbench Flow | What 's UVM? | Why UVM? | Basic UVM Hierarchy YOU should know

System Tasks in Verilog | in Tamil | with English SUB

System Tasks in Verilog | in Tamil | with English SUB

Enumeration in System Verilog | What it is | Built-in methods (with demo)

Enumeration in System Verilog | What it is | Built-in methods (with demo)