Канал: Codasip

With great power comes great responsibility - Customizing your processor with verification in mind

With great power comes great responsibility - Customizing your processor with verification in mind

A short overview: Codasip Studio Compiler

A short overview: Codasip Studio Compiler

A short overview: Codasip Studio Profiler

A short overview: Codasip Studio Profiler

A short overview: How to relate generated RTL back to CodAL

A short overview: How to relate generated RTL back to CodAL

A short overview: Getting started with Codasip Studio & CodAL

A short overview: Getting started with Codasip Studio & CodAL

RISC-V Summit Europe highlights

RISC-V Summit Europe highlights

DAC Demo: AI Inference for anomaly detection on an embedded RISC-V core

DAC Demo: AI Inference for anomaly detection on an embedded RISC-V core

RISC-V Summit Europe day 1

RISC-V Summit Europe day 1

Codasip Studio Demo

Codasip Studio Demo

How do vector length agnostic architectures work?

How do vector length agnostic architectures work?

Toby Wenman talks about Vector load/store segment instructions

Toby Wenman talks about Vector load/store segment instructions

Codasip Demo - Accelerated DSP on a Customized RISC-V Core

Codasip Demo - Accelerated DSP on a Customized RISC-V Core

Codasip at Embedded World 2024 - meet our partners

Codasip at Embedded World 2024 - meet our partners

Embedded World 2024 day 2 highlights

Embedded World 2024 day 2 highlights

CHERI Demo at Embedded World 2024

CHERI Demo at Embedded World 2024

Embedded World 2024 day 1 highlights

Embedded World 2024 day 1 highlights

Carl Shaw - CHERI protection & software

Carl Shaw - CHERI protection & software

Carl Shaw - Compartmentalization CHERI

Carl Shaw - Compartmentalization CHERI

Ben Fletcher - CPU performance modelling

Ben Fletcher - CPU performance modelling

Carl Shaw - What is CHERI and why is it necessary?

Carl Shaw - What is CHERI and why is it necessary?

Jamie Melling - Understanding RISC-V virtual memory

Jamie Melling - Understanding RISC-V virtual memory

Tariq Kurd - Efficiently managing tagged memory for RISC-V

Tariq Kurd - Efficiently managing tagged memory for RISC-V

Tariq Kurd - A730+CHERI

Tariq Kurd - A730+CHERI

Codasip at RISC-V Summit US 2023 – Day 2

Codasip at RISC-V Summit US 2023 – Day 2

Codasip at RISC-V Summit US 2023 – Day 1

Codasip at RISC-V Summit US 2023 – Day 1

Codasip at Design Automation Conference 2023 DAC

Codasip at Design Automation Conference 2023 DAC

RISC-V customization demo: AI-based image denoising

RISC-V customization demo: AI-based image denoising

RISC-V Summit Europe 2023 - Codasip summary

RISC-V Summit Europe 2023 - Codasip summary

Codasip’s approach to custom compute

Codasip’s approach to custom compute

Architecting ambitions with custom compute #ew23 #embeddedworld

Architecting ambitions with custom compute #ew23 #embeddedworld

Codasip at Embedded World 2023 - Day 2

Codasip at Embedded World 2023 - Day 2

Codasip at Embedded World 2023 - Day 1

Codasip at Embedded World 2023 - Day 1

Codasip demo - Embedded World 2023 - Dual Core LockStep

Codasip demo - Embedded World 2023 - Dual Core LockStep

Codasip demo - Embedded World 2023 - FIR filter

Codasip demo - Embedded World 2023 - FIR filter

Architect your ambition - Codasip

Architect your ambition - Codasip

Assignment 11: Adding a Custom Instruction

Assignment 11: Adding a Custom Instruction

Assignment 11: Checkpoint 3: Verify the new instruction in your CA model

Assignment 11: Checkpoint 3: Verify the new instruction in your CA model

Assignment 11: Checkpoint 2: Verifying that the compiler is using your new instruction

Assignment 11: Checkpoint 2: Verifying that the compiler is using your new instruction

Assignment 11: Checkpoint 1: Determining a custom instruction to accelerate bubble_sort.c

Assignment 11: Checkpoint 1: Determining a custom instruction to accelerate bubble_sort.c

FAQ: No Profile Generated

Assignment 10: Checkpoint 5: Realizing Performance via Prediction

Assignment 10: Checkpoint 5: Realizing Performance via Prediction

Assignment 10: Checkpoint 4: Using prediction_test.s to verify branch prediction

Assignment 10: Checkpoint 4: Using prediction_test.s to verify branch prediction

Assignment 10: Checkpoint 3: Profiling the Bubble Sort c-program before adding branch prediction

Assignment 10: Checkpoint 3: Profiling the Bubble Sort c-program before adding branch prediction

Assignment 10: Checkpoint 2: How many clock cycles after JAL prediction?

Assignment 10: Checkpoint 2: How many clock cycles after JAL prediction?

Assignment 10: Checkpoint 1: How many clock cycles before Jump prediction?

Assignment 10: Checkpoint 1: How many clock cycles before Jump prediction?

Assignment 10: Branch Prediction

Assignment 10: Branch Prediction

FAQ: Sign Extending Signals

FAQ: Sign Extending Signals

Assignment 4: Block Diagram

Assignment 4: Block Diagram

FAQ: Finding your CA model to debug

FAQ: Finding your CA model to debug

FAQ: Debugger: How to Fix Window Flickering

FAQ: Debugger: How to Fix Window Flickering

Assignment 3: Using ip.conf to Validate your Regression Test

Assignment 3: Using ip.conf to Validate your Regression Test

Assignment 2: Checkpoint 3: Writing the routine in RISCV32I machine code

Assignment 2: Checkpoint 3: Writing the routine in RISCV32I machine code

FAQ: Extended Register and Memory Views

FAQ: Extended Register and Memory Views

FAQ: Minimizing open tabs while viewing thru files

FAQ: Minimizing open tabs while viewing thru files

FAQ: Export and Import zip files

FAQ: Export and Import zip files

Codasip booth at the 2022 RISC-V Summit

Codasip booth at the 2022 RISC-V Summit

Get ready to meet Codasip at the RISC-V Summit 2022

Get ready to meet Codasip at the RISC-V Summit 2022

Assignment 9: Checkpoint 4: Running your first C-program

Assignment 9: Checkpoint 4: Running your first C-program

Assignment 9: Checkpoint 1: Validating LUI and AUIPC Instructions

Assignment 9: Checkpoint 1: Validating LUI and AUIPC Instructions

Assignment 9: C compiler Generation

Assignment 9: C compiler Generation

FAQ: Memory Encode Decode constructs

FAQ: Memory Encode Decode constructs

Assignment 8: Checkpoint 2: Validating Load Operations

Assignment 8: Checkpoint 2: Validating Load Operations

Assignment 8: Checkpoint 1: Validating Store Operations

Assignment 8: Checkpoint 1: Validating Store Operations

Assignment 8: Load and Store Instructions

Assignment 8: Load and Store Instructions

Codasip delivers custom RISC-V processing to SiliconArts ray-tracing GPUs

Codasip delivers custom RISC-V processing to SiliconArts ray-tracing GPUs

Assignment 7: Checkpoint 1: Validating branch instructions

Assignment 7: Checkpoint 1: Validating branch instructions

Assignment 7: Branch and Jump Instructions

Assignment 7: Branch and Jump Instructions

Assignment 3: Regression Testing

Assignment 3: Regression Testing

FAQ: enums and switch statements

FAQ: enums and switch statements

FAQ: Addressing Memory and Memory View

FAQ: Addressing Memory and Memory View

Assignment 6: Data Hazard Detection and Forwarding

Assignment 6: Data Hazard Detection and Forwarding

FAQ: bitsizeof() macro

FAQ: bitsizeof() macro

Assignment 6: Checkpoint 1: Validating data-hazard detection and forwarding

Assignment 6: Checkpoint 1: Validating data-hazard detection and forwarding

Assignment 2: Power of Abstraction

Assignment 2: Power of Abstraction

Assignment 2: Checkpoint 2: Writing the routine in RISCV32i assembly language

Assignment 2: Checkpoint 2: Writing the routine in RISCV32i assembly language

FAQ: Helpful c program debug hints

FAQ: Helpful c program debug hints

Assignment 2: Checkpoint 1: Writing the routine in c

Assignment 2: Checkpoint 1: Writing the routine in c

Assignment 5: Imaging Software into Hardware

Assignment 5: Imaging Software into Hardware

Assignment 5: Checkpoint 1: Using the addi_assemby_test

Assignment 5: Checkpoint 1: Using the addi_assemby_test

Assignment 5: Data Path and Instruction Decoder

Assignment 5: Data Path and Instruction Decoder

FAQ: Why won't my breakpoint go where I want it to go?

FAQ: Why won't my breakpoint go where I want it to go?

Assignment 5: Signal and Register Types

Assignment 5: Signal and Register Types

Assignment 5: Parsing using Bit Extraction and Concatenation

Assignment 5: Parsing using Bit Extraction and Concatenation

FAQ: Not Declared in this Scope

FAQ: Not Declared in this Scope

FAQ: Functional Unit has to be Combinational Logic

FAQ: Functional Unit has to be Combinational Logic

FAQ: Decoding a CA Compiler Error Message

FAQ: Decoding a CA Compiler Error Message

FAQ: Changing Codasip Studio Color Theme

FAQ: Changing Codasip Studio Color Theme

Assignment 1: Checkpoint 1

Assignment 1: Checkpoint 1

FAQ: "No SDK to Assign" Error in Codasip Studio

FAQ: "No SDK to Assign" Error in Codasip Studio

FAQ: "Error Duplicate Symbol: _start" in Codasip Studio

FAQ: "Error Duplicate Symbol: _start" in Codasip Studio

FAQ: "Debugger start but no program to debug" Error in Codasip Studio

FAQ: "Debugger start but no program to debug" Error in Codasip Studio

FAQ: "Debugger Does Not Launch" Error in Codasip Studio

FAQ: "Debugger Does Not Launch" Error in Codasip Studio

FAQ: "No Such File or Directory" Build Error in Codasip Studio

FAQ: "No Such File or Directory" Build Error in Codasip Studio

Assignment 1: Introduction to Computer Organization

Assignment 1: Introduction to Computer Organization

Codasip at Embedded World 2022 - interview by RISC-V International

Codasip at Embedded World 2022 - interview by RISC-V International

Codasip at DAC 2022 - summary

Codasip at DAC 2022 - summary

Customizing RISC-V cores to accelerate neural networks | Jon Taylor at EW22

Customizing RISC-V cores to accelerate neural networks | Jon Taylor at EW22

I Fought the Law and the Law Lost: Moore’s Law, Dennard Scaling & RISC-V | Rupert Baines at EW22

I Fought the Law and the Law Lost: Moore’s Law, Dennard Scaling & RISC-V | Rupert Baines at EW22

Design for Differentiation - Architecture licenses in RISC-V | Filip Benna at EW22

Design for Differentiation - Architecture licenses in RISC-V | Filip Benna at EW22

Codasip stand at Embedded World 2022 - RISC-V pavilion

Codasip stand at Embedded World 2022 - RISC-V pavilion

Codasip booth at Embedded World 2022 - Hall 2

Codasip booth at Embedded World 2022 - Hall 2

Codasip at Embedded World 2022 - Day 1

Codasip at Embedded World 2022 - Day 1

Codasip at Embedded World 2022 - Day 2

Codasip at Embedded World 2022 - Day 2

Codasip at Embedded World 2022 - Day 3

Codasip at Embedded World 2022 - Day 3

Codasip | RISC-V Summit 2021 | Virtual Booth Video

Codasip | RISC-V Summit 2021 | Virtual Booth Video

Welcome to Codasip

Welcome to Codasip

Senior FRONTEND Developer (QA) at Codasip

Senior FRONTEND Developer (QA) at Codasip

Senior PYTHON Developer (QA) at Codasip

Senior PYTHON Developer (QA) at Codasip

Codasip vlog 2, part 3: The CodAL Language

Codasip vlog 2, part 3: The CodAL Language

Codasip vlog 2, part 2: Designing Domain-Specific Accelerators

Codasip vlog 2, part 2: Designing Domain-Specific Accelerators

Codasip vlog 2, part 1: Introduction to Domain-Specific Accelerators

Codasip vlog 2, part 1: Introduction to Domain-Specific Accelerators

Codasip vlog 1, part 7: Processor Design & RISC-V Summary & Bonus!

Codasip vlog 1, part 7: Processor Design & RISC-V Summary & Bonus!

Codasip vlog 1, part 6b: PPA numbers – how to improve them?

Codasip vlog 1, part 6b: PPA numbers – how to improve them?

Codasip vlog 1, part 6a: PPA &processor benchmarks – how to make sense of them?

Codasip vlog 1, part 6a: PPA &processor benchmarks – how to make sense of them?

Codasip vlog 1, part 5: Codasip's application processors

Codasip vlog 1, part 5: Codasip's application processors

Codasip's story & unique technology for processor customization – RISC-V Summit 2020

Codasip's story & unique technology for processor customization – RISC-V Summit 2020

Codasip vlog 1, part 4: What is needed to support an OS?

Codasip vlog 1, part 4: What is needed to support an OS?

Codasip vlog 1, part 3: What is Processor Complexity?

Codasip vlog 1, part 3: What is Processor Complexity?

Joint presentation by Codasip & Metrics Design Automation at the RISC-V Global Forum 2020

Joint presentation by Codasip & Metrics Design Automation at the RISC-V Global Forum 2020