Канал: Sarah Harris

DDCArv VGA Lecture

DDCArv VGA Lecture

VGA demo

VGA demo

DDCArv Ch8 - Part 13: Virtual Memory Summary

DDCArv Ch8 - Part 13: Virtual Memory Summary

DDCArv Ch8 - Part 12: TLBs

DDCArv Ch8 - Part 12: TLBs

DDCArv Ch8 -Part 11: Page Tables

DDCArv Ch8 -Part 11: Page Tables

DDCArv Ch8 - Part 10: Address Translation

DDCArv Ch8 - Part 10: Address Translation

DDCArv Ch8 - Part 9: Virtual Memory Introduction

DDCArv Ch8 - Part 9: Virtual Memory Introduction

DDCArv Ch8 - Part 8: Cache Summary

DDCArv Ch8 - Part 8: Cache Summary

DDCArv Ch8 - Part 7: LRU Replacement

DDCArv Ch8 - Part 7: LRU Replacement

DDCArv Ch8 - Part 1: Memory System Introduction

DDCArv Ch8 - Part 1: Memory System Introduction

DDCArv Ch8 - Part 6: Spatial Locality

DDCArv Ch8 - Part 6: Spatial Locality

DDCArv Ch8 - Part 5: Associative Caches

DDCArv Ch8 - Part 5: Associative Caches

DDCArv Ch8 - Part 4: Direct-Mapped Caches

DDCArv Ch8 - Part 4: Direct-Mapped Caches

DDCArv Ch8 - Part 3: Cache Introduction

DDCArv Ch8 - Part 3: Cache Introduction

DDCArv Ch8 - Part 2: Performance

DDCArv Ch8 - Part 2: Performance

DDCA Ch2: DeMorgan's Theorem Examples

DDCA Ch2: DeMorgan's Theorem Examples

DDCA Ch2: Proving Boolean Theorems

DDCA Ch2: Proving Boolean Theorems

DDCA Ch2: Simplifying Boolean Equations - Examples

DDCA Ch2: Simplifying Boolean Equations - Examples

DDCA Ch6 - Part 15 Machine Language Introduction

DDCA Ch6 - Part 15 Machine Language Introduction

DDCA Ch6 - Part 16 Machine Language More Formats

DDCA Ch6 - Part 16 Machine Language More Formats

DDCA Ch2 - Part 15: Timing of Combinational Logic

DDCA Ch2 - Part 15: Timing of Combinational Logic

DDCA Ch2 - Part 14: Decoders

DDCA Ch2 - Part 14: Decoders

DDCA Ch2 - Part 13: Multiplexers

DDCA Ch2 - Part 13: Multiplexers

DDCA Ch2 - Part 12: K-Maps with Don't Cares

DDCA Ch2 - Part 12: K-Maps with Don't Cares

DDCA Ch2 - Part 11: Karnaugh Maps (K-Maps)

DDCA Ch2 - Part 11: Karnaugh Maps (K-Maps)

DDCA Ch2 - Part 10: X's and Z's, Oh My

DDCA Ch2 - Part 10: X's and Z's, Oh My

DDCA Ch2 - Part 9: Bubble Pushing

DDCA Ch2 - Part 9: Bubble Pushing

DDCA Ch2 - Part 8: From Logic to Gates

DDCA Ch2 - Part 8: From Logic to Gates

DDCA Ch2 - Part 7: Simplifying Boolean Equations

DDCA Ch2 - Part 7: Simplifying Boolean Equations

DDCA Ch2 - Part 6: Boolean Theorems of Several Variables

DDCA Ch2 - Part 6: Boolean Theorems of Several Variables

DDCA Ch2 - Part 5: Boolean Theorems of One Variable

DDCA Ch2 - Part 5: Boolean Theorems of One Variable

DDCA Ch2 - Part 4: Boolean Axioms

DDCA Ch2 - Part 4: Boolean Axioms

DDCA Ch2 - Part 3: Boolean Equations

DDCA Ch2 - Part 3: Boolean Equations

DDCA Ch2 - Part 2: Combinational Circuits

DDCA Ch2 - Part 2: Combinational Circuits

DDCA Ch2 - Part 1: Combinational Logic Introduction

DDCA Ch2 - Part 1: Combinational Logic Introduction

DDCA Ch1 - Part 11: Power Consumption of Digital Circuits

DDCA Ch1 - Part 11: Power Consumption of Digital Circuits

DDCA Ch1 - Part 10: Gates FromTransistors

DDCA Ch1 - Part 10: Gates FromTransistors

DDCA Ch1 - Part 9: Transistors

DDCA Ch1 - Part 9: Transistors

DDCA Ch1 - Part 8: Logic Gates

DDCA Ch1 - Part 8: Logic Gates

DDCA Ch1 - Part 7: Extension

DDCA Ch1 - Part 7: Extension

DDCA Ch1 - Part 6: Signed Binary Numbers

DDCA Ch1 - Part 6: Signed Binary Numbers

DDCA Ch1- Part 5: Binary Addition

DDCA Ch1- Part 5: Binary Addition

DDCA Ch1 - Part 4: Bytes, Nibbles & All That Jazz

DDCA Ch1 - Part 4: Bytes, Nibbles & All That Jazz

DDCA Ch1 - Part 3: Hexadecimal Numbers

DDCA Ch1 - Part 3: Hexadecimal Numbers

DDCA Ch1 - Part 2: Unsigned Binary Numbers

DDCA Ch1 - Part 2: Unsigned Binary Numbers

DDCA Ch1 - Part 1: Managing Complexity

DDCA Ch1 - Part 1: Managing Complexity

DDCA Ch1 - Part 0: Introduction to Digital Design

DDCA Ch1 - Part 0: Introduction to Digital Design

DDCA Ch7 - Part 12: Multicycle Processor Performance

DDCA Ch7 - Part 12: Multicycle Processor Performance

DDCA Ch7 - Part 1: Microarchitecture Introduction

DDCA Ch7 - Part 1: Microarchitecture Introduction

DDCA Ch7 - Part 2: RISC-V Single-Cycle Processor Datapath: lw

DDCA Ch7 - Part 2: RISC-V Single-Cycle Processor Datapath: lw

DDCA Ch7 - Part 3: RISC-V Single-Cycle Processor Datapath: Extending Instructions

DDCA Ch7 - Part 3: RISC-V Single-Cycle Processor Datapath: Extending Instructions

DDCA Ch7 - Part 4: RISC-V Single-Cycle Processor: Control

DDCA Ch7 - Part 4: RISC-V Single-Cycle Processor: Control

DDCA Ch7 - Part 5: RISC-V Single-Cycle Processor: Adding Instructions

DDCA Ch7 - Part 5: RISC-V Single-Cycle Processor: Adding Instructions

DDCA Ch7 - Part 6: RISC-V Single-Cycle Performance

DDCA Ch7 - Part 6: RISC-V Single-Cycle Performance

DDCA Ch7 - Part 6a: RISC-V Processor Test Program & Testbench

DDCA Ch7 - Part 6a: RISC-V Processor Test Program & Testbench

DDCA Ch7 - Part 6b: RISC-V Single-Cycle Processor Verilog

DDCA Ch7 - Part 6b: RISC-V Single-Cycle Processor Verilog

DDCA Ch7 - Part 7: Multicycle Processor: Datapath for lw

DDCA Ch7 - Part 7: Multicycle Processor: Datapath for lw

DDCA Ch7 = Part 16: Pipelined Processor Performance

DDCA Ch7 = Part 16: Pipelined Processor Performance

DDCA Ch7 - Part 17" Advanced Microarchitecture

DDCA Ch7 - Part 17" Advanced Microarchitecture

DDCA Ch7 - Part 18: Superscalar & Out of Order Processors

DDCA Ch7 - Part 18: Superscalar & Out of Order Processors

DDCA Ch7 - Part 19: Multithreading & Multiprocessors

DDCA Ch7 - Part 19: Multithreading & Multiprocessors

DDCA Ch7 - Part 13: Pipelined Processor

DDCA Ch7 - Part 13: Pipelined Processor

DDCA Ch7 - Part 14: Pipelined Processor Data Hazards

DDCA Ch7 - Part 14: Pipelined Processor Data Hazards

DDCA Ch7 - Part 15: Pipelined Processor Control Hazards

DDCA Ch7 - Part 15: Pipelined Processor Control Hazards

DDCA Ch9 - Part 1: Embedded Systems Introduction

DDCA Ch9 - Part 1: Embedded Systems Introduction

DDCA Ch9 - Part 2: RISC-V Microcontrollers

DDCA Ch9 - Part 2: RISC-V Microcontrollers

DDCA Ch9 - Part 3: Memory-Mapped I/O

DDCA Ch9 - Part 3: Memory-Mapped I/O

DDCA Ch9 - Part 4: General-Purpose I/O (GPIO)

DDCA Ch9 - Part 4: General-Purpose I/O (GPIO)

DDCA Ch9 - Part 5: RISC-V Device Driver

DDCA Ch9 - Part 5: RISC-V Device Driver

DDCA Ch9 - Part 6: Timers

DDCA Ch9 - Part 6: Timers

DDCA Ch9 - Part 7: Morse Code Example

DDCA Ch9 - Part 7: Morse Code Example

DDCA Ch9 - Part 8: Interfacing

DDCA Ch9 - Part 8: Interfacing

DDCA Ch9 - Part 9: SPI

DDCA Ch9 - Part 9: SPI

DDCA Ch9 - Part 10: SPI Accelerometer Example

DDCA Ch9 - Part 10: SPI Accelerometer Example

DDCA Ch6 - Part 15: RISC-V Machine Instructions: R-Type

DDCA Ch6 - Part 15: RISC-V Machine Instructions: R-Type

DDCA Ch6 - Part 1: RISC-V Architecture Introduction

DDCA Ch6 - Part 1: RISC-V Architecture Introduction

DDCA Ch6 - Part 2: RISC-V Instructions

DDCA Ch6 - Part 2: RISC-V Instructions

DDCA Ch6 - Part 3: RISC-V Operands

DDCA Ch6 - Part 3: RISC-V Operands

DDCA Ch6 - Part 4: RISC-V Memory Instructions

DDCA Ch6 - Part 4: RISC-V Memory Instructions

DDCA Ch6 - Part 5: RISC-V Immediates (Constants)

DDCA Ch6 - Part 5: RISC-V Immediates (Constants)

DDCA Ch6 - Part 6: Logical Instructions

DDCA Ch6 - Part 6: Logical Instructions

DDCA Ch6 - Part 7: RISC-V Multiplication & Division Instructions

DDCA Ch6 - Part 7: RISC-V Multiplication & Division Instructions

DDCA Ch6 - Part 8: Branches

DDCA Ch6 - Part 8: Branches

DDCA Ch6 - Part 9: RISC-V Conditional Statements

DDCA Ch6 - Part 9: RISC-V Conditional Statements

DDCA Ch6 - Part 10: Arrays

DDCA Ch6 - Part 10: Arrays

DDCA Ch6 - Part 11: RISC-V Functions

DDCA Ch6 - Part 11: RISC-V Functions

DDCA Ch6 - Part 12: The Stack

DDCA Ch6 - Part 12: The Stack

DDCA Ch6 - Part 13: Recursive Functions

DDCA Ch6 - Part 13: Recursive Functions

DDCA Ch6 - Part 14: Jumps & Pseudoinstructions

DDCA Ch6 - Part 14: Jumps & Pseudoinstructions

DDCA Ch6 - Part 20: Big-Endian and Little-Endian Memory

DDCA Ch6 - Part 20: Big-Endian and Little-Endian Memory

DDCA Ch6 - Part 16: More Machine Language Formats

DDCA Ch6 - Part 16: More Machine Language Formats

DDCA Ch6 - Part 17: RISC-V Immediate Encodings

DDCA Ch6 - Part 17: RISC-V Immediate Encodings

DDCA Ch6 - Part 18: Decoding Machine Language & Addressing Operands

DDCA Ch6 - Part 18: Decoding Machine Language & Addressing Operands

DDCA Ch6 - Part 19: Compiling, Assembling, and Loading Programs

DDCA Ch6 - Part 19: Compiling, Assembling, and Loading Programs

DDCA Ch6 - Part 22: RISC-V Compressed Instructions

DDCA Ch6 - Part 22: RISC-V Compressed Instructions

DDCA Ch6 - Part 23: RISC-V Floating-Point Instructions

DDCA Ch6 - Part 23: RISC-V Floating-Point Instructions

DDCA Ch6 - Part 21: Signed and Unsigned RISC-V Instructions

DDCA Ch6 - Part 21: Signed and Unsigned RISC-V Instructions

DDCA Ch7 - Part 11: Extending the RISC-V Multicycle Processor

DDCA Ch7 - Part 11: Extending the RISC-V Multicycle Processor

DDCA Ch7 - Part 10: RISC-V Multicycle Processor Control: Other Instructions

DDCA Ch7 - Part 10: RISC-V Multicycle Processor Control: Other Instructions

DDCA Ch7 - Part 9: RISC-V Multicycle Processor Control: lw

DDCA Ch7 - Part 9: RISC-V Multicycle Processor Control: lw

DDCA Ch7 - Part 6c Processor Tie Celebration

DDCA Ch7 - Part 6c Processor Tie Celebration

DDCA Ch7 - part 8: RISC-V Multicycle Processor - Other Instructions

DDCA Ch7 - part 8: RISC-V Multicycle Processor - Other Instructions

RVfpga (Paper #140) FPL Aug2021 Harris Chaver Presentation

RVfpga (Paper #140) FPL Aug2021 Harris Chaver Presentation

WCAE '21 - Paper 8: Digital Design and RISC-V Computer Architecture Textbook:Harris & Harris

WCAE '21 - Paper 8: Digital Design and RISC-V Computer Architecture Textbook:Harris & Harris

DDCA Ch3 - Part 7: Introduction to Synchronous Sequential Logic

DDCA Ch3 - Part 7: Introduction to Synchronous Sequential Logic

DDCA Ch3 - Part 8: Introduction to Finite State Machines (FSMs)

DDCA Ch3 - Part 8: Introduction to Finite State Machines (FSMs)

DDCA Ch3 - Part 9: Moore FSM Example 1

DDCA Ch3 - Part 9: Moore FSM Example 1

DDCA Ch3 - Part 10: Moore FSM Example 2

DDCA Ch3 - Part 10: Moore FSM Example 2

DDCA Ch3 - Part 11: Mealy FSM Example

DDCA Ch3 - Part 11: Mealy FSM Example

DDCA Ch3 - Part 12: Factored FSMs

DDCA Ch3 - Part 12: Factored FSMs

DDCA Ch3 - Part 13: Timing

DDCA Ch3 - Part 13: Timing

DDCA Ch3 - Part 14: ClockSkew

DDCA Ch3 - Part 14: ClockSkew

DDCA Ch3 - Part 16: Parallelism

DDCA Ch3 - Part 16: Parallelism

DDCA Ch1 - Part 3: Hexadecimal Numbers

DDCA Ch1 - Part 3: Hexadecimal Numbers

DDCA Ch3 - Part 1: Intro to Sequential Logic

DDCA Ch3 - Part 1: Intro to Sequential Logic

DDCA Ch3 - Part 2: Bistable Circuit

DDCA Ch3 - Part 2: Bistable Circuit

DDCA Ch3 - Part 3: SR Latch

DDCA Ch3 - Part 3: SR Latch

DDCA Ch3 - Part 4: D Latch

DDCA Ch3 - Part 4: D Latch

DDCA Ch3 - Part 5: D Flip-Flop

DDCA Ch3 - Part 5: D Flip-Flop

DDCA Ch3 - Part 6: Flop Variations

DDCA Ch3 - Part 6: Flop Variations

DDCA Ch2 - Part 9: Xs and Zs

DDCA Ch2 - Part 9: Xs and Zs

DDCA Ch2 - Part 1: Combinational Circuits

DDCA Ch2 - Part 1: Combinational Circuits

DDCA Ch2 - Part 10: K-Maps

DDCA Ch2 - Part 10: K-Maps

DDCA Ch2 - Part 2: Boolean Equations: SOP and POS Forms

DDCA Ch2 - Part 2: Boolean Equations: SOP and POS Forms

DDCA Ch2 - Part 13: Decoders

DDCA Ch2 - Part 13: Decoders

DDCA Ch2 - Part 3: Boolean Axioms & Theorems

DDCA Ch2 - Part 3: Boolean Axioms & Theorems

DDCA Ch2 - Part 12: Multiplexers

DDCA Ch2 - Part 12: Multiplexers

DDCA Ch2 - Part 7: Two-Level Logic

DDCA Ch2 - Part 7: Two-Level Logic

DDCA Ch2 - Part 6: From Logic To Gates

DDCA Ch2 - Part 6: From Logic To Gates

DDCA Ch2 - Part 11: K-Maps with Don't Cares

DDCA Ch2 - Part 11: K-Maps with Don't Cares

DDCA Ch2 - Part 5: Simplifying Equations

DDCA Ch2 - Part 5: Simplifying Equations

DDCA Ch2 - Part 4: Boolean Theorems of Multiple Variables

DDCA Ch2 - Part 4: Boolean Theorems of Multiple Variables

DDCA Ch1 - Part 5: Signed Numbers

DDCA Ch1 - Part 5: Signed Numbers

DDCA Ch2 - Part 8: Bubble Pushing

DDCA Ch2 - Part 8: Bubble Pushing

DDCA Ch1 - Part 7: Logic Gates

DDCA Ch1 - Part 7: Logic Gates

DDCA Ch1 - Part 2: Unsigned Binary Numbers

DDCA Ch1 - Part 2: Unsigned Binary Numbers

DDCA Ch1 - Part 6: Extension

DDCA Ch1 - Part 6: Extension

DDCA Ch1 - Part 4: Addition

DDCA Ch1 - Part 4: Addition

DDCA Ch1 - Part 1: Managing Complexity

DDCA Ch1 - Part 1: Managing Complexity

DDCA Ch1 - Part 3: Hexadecimal Numbers

DDCA Ch1 - Part 3: Hexadecimal Numbers

DDCA Ch6 - Part 19: Compiling and Loading a Program

DDCA Ch6 - Part 19: Compiling and Loading a Program

DDCA Ch6 - Part 16: More Machine Language Formats

DDCA Ch6 - Part 16: More Machine Language Formats

DDCA Ch6 - Part 17: Immediate Encodings

DDCA Ch6 - Part 17: Immediate Encodings

DDCA Ch6 - Part 15: Machine Language

DDCA Ch6 - Part 15: Machine Language

DDCA Ch6 - Part 18: Translating Machine Code

DDCA Ch6 - Part 18: Translating Machine Code

DDCA Ch6 - Part 20: Endianness

DDCA Ch6 - Part 20: Endianness

DDCA Ch6 - Part 13: Recursive Functions

DDCA Ch6 - Part 13: Recursive Functions

DDCA Ch6 - Part 12: The Stack

DDCA Ch6 - Part 12: The Stack

DDCA Ch6 - Part 6: Logical & Shift Instructions

DDCA Ch6 - Part 6: Logical & Shift Instructions

DDCA Ch6 - Part 7: Multiplication & Division Instructions

DDCA Ch6 - Part 7: Multiplication & Division Instructions

DDCA Ch6 - Part 9: Conditional Statements & Loops

DDCA Ch6 - Part 9: Conditional Statements & Loops

DDCA Ch6 - Part 11: Function Calls

DDCA Ch6 - Part 11: Function Calls

DDCA Ch6 - Part 14: More Jumps & PseudoInstructions

DDCA Ch6 - Part 14: More Jumps & PseudoInstructions

DDCA Ch6 - Part 10: Accessing Arrays

DDCA Ch6 - Part 10: Accessing Arrays

DDCA Ch6 - Part 8: Branches & Jumps

DDCA Ch6 - Part 8: Branches & Jumps

DDCA Ch6 - Part 5: Generating Constants

DDCA Ch6 - Part 5: Generating Constants

DDCA Ch6 - Part 4: Memory

DDCA Ch6 - Part 4: Memory

DDCA Ch6 - Part 3: Operands

DDCA Ch6 - Part 3: Operands

DDCA Ch6 - Part 2: Instructions

DDCA Ch6 - Part 2: Instructions

DDCA Ch6 - Part 1: Architecture Introduction

DDCA Ch6 - Part 1: Architecture Introduction

DDCA Ch5 - Part 7: ALUs

DDCA Ch5 - Part 7: ALUs

DDCA Ch5 - Part 8: Shifters, Multipliers, & Dividers

DDCA Ch5 - Part 8: Shifters, Multipliers, & Dividers

DDCA Ch5 - Part 9: Fixed Point Numbers

DDCA Ch5 - Part 9: Fixed Point Numbers

DDCA Ch5 - Part 10: Floating Point Numbers

DDCA Ch5 - Part 10: Floating Point Numbers

DDCA Ch5 - Part 11: Floating Point Addition

DDCA Ch5 - Part 11: Floating Point Addition

DDCA Ch5 - Part 12: Counters & Shift Registers

DDCA Ch5 - Part 12: Counters & Shift Registers

DDCA Ch5 - Part 13: Memory Introduction

DDCA Ch5 - Part 13: Memory Introduction

DDCA Ch5 - Part 14: RAM

DDCA Ch5 - Part 14: RAM

DDCA Ch5 - Part 16: SystemVerilog Memories

DDCA Ch5 - Part 16: SystemVerilog Memories

DDCA Ch5 - Part 17: Logic Arrays

DDCA Ch5 - Part 17: Logic Arrays

EGG 101 - 10/9/2020 - Dr. Harris

EGG 101 - 10/9/2020 - Dr. Harris

DDCA Ch5 - Part 5: Prefix Adders

DDCA Ch5 - Part 5: Prefix Adders

DDCA Ch5 - Part 6: Subtractors & Comparators

DDCA Ch5 - Part 6: Subtractors & Comparators

DDCA Ch5: Part 4 - Carry Lookahead Adders

DDCA Ch5: Part 4 - Carry Lookahead Adders

DDCA Ch5 - Part 3: Ripple Carry Adders

DDCA Ch5 - Part 3: Ripple Carry Adders

DDCA Ch5 - Part 2: Adders Introduction

DDCA Ch5 - Part 2: Adders Introduction

DDCA Ch5: Part 1: Digital Building Blocks Introduction

DDCA Ch5: Part 1: Digital Building Blocks Introduction

DDCA Ch5 - Part 15: ROMs (Read Only Memories)

DDCA Ch5 - Part 15: ROMs (Read Only Memories)

DDCA Ch3- Part 21: Parallelism

DDCA Ch3- Part 21: Parallelism

DDCA Ch3 - Part 11: StateEncodings

DDCA Ch3 - Part 11: StateEncodings

DDCA Ch3 - Part 12: Mealy FSMs

DDCA Ch3 - Part 12: Mealy FSMs

DDCA Ch3 - Part 13: Factored FSMs

DDCA Ch3 - Part 13: Factored FSMs

DDCA Ch3 - Part 14: Timing

DDCA Ch3 - Part 14: Timing

DDCA Ch3 - Part 15: Setup Time Constraint

DDCA Ch3 - Part 15: Setup Time Constraint

DDCA Ch3 - Part 16: Hold Time Constraint

DDCA Ch3 - Part 16: Hold Time Constraint

DDCA Ch3 - Part 17: Timing Analysis

DDCA Ch3 - Part 17: Timing Analysis

DDCA Ch3 - Part 18: Skew

DDCA Ch3 - Part 18: Skew

DDCA Ch3 - Part 19: Metastability

DDCA Ch3 - Part 19: Metastability

DDCA Ch3 - Part 20: Synchronizers

DDCA Ch3 - Part 20: Synchronizers

DDCA Ch4 - Part 2: Combinational logic in SystemVerilog

DDCA Ch4 - Part 2: Combinational logic in SystemVerilog

DDCA Ch4 - Part 3: Delays in SystemVerilog simulations

DDCA Ch4 - Part 3: Delays in SystemVerilog simulations

DDCA Ch4 - Part 4: Sequential Logic in SystemVerilog

DDCA Ch4 - Part 4: Sequential Logic in SystemVerilog

DDCA Ch4 - Part 5: Combinational logic using always blocks

DDCA Ch4 - Part 5: Combinational logic using always blocks

DDCA Ch4 - Part 6: SystemVerilog Assignments

DDCA Ch4 - Part 6: SystemVerilog Assignments

DDCA Ch4 - Part 7: FSMs

DDCA Ch4 - Part 7: FSMs

DDCA Ch4 - Part 8: Parameterized Modules

DDCA Ch4 - Part 8: Parameterized Modules

DDCA Ch4 - Part 9: Testbenches

DDCA Ch4 - Part 9: Testbenches

DDCA Ch4 - Part 1: SystemVerilog Introduction

DDCA Ch4 - Part 1: SystemVerilog Introduction

CpE 100 Module 21: Finite State Machines

CpE 100 Module 21: Finite State Machines

CpE 100 Module 20: Registers & Other Flip-Flops

CpE 100 Module 20: Registers & Other Flip-Flops