Azita Emami 2013-2014 Seminar Series
December 4, 2013

The scalability of CMOS technology has driven computation into a diverse range of applications across the power consumption, performance and size spectra. Communication is a necessary adjunct to computation, and whether in the context of high-performance computing, mobile devices or biomedical implants, chip-to-chip communication can take up a significant portion of the overall system power budget. A single interconnect methodology cannot address such a broad range of requirements efficiently. Nevertheless, there are a number of interesting design concepts that can facilitate efficient interconnect design, no matter what the application; this talk seeks to elucidate these concepts through design examples at both ends of the power/performance spectra. In particular we present efficient transceivers for parallel optical interconnects that can take advantage of recent advances in silicon photonic devices. Novel low-power clocking techniques, which are essential for synchronous data communication, will be discussed as well. We conclude this presentation with a brief discussion of limitations of on-chip signaling, our proposed solutions and applications of proximity communication in minimally invasive biomedical implants.

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