In this episode, Randy White and Stephen Slater of Keysight Technologies join me to take a deep dive into DDR5 Memory and how to best design and simulate memory. We also talk about understanding and tapping into the full ecosystem that supports this technology and will help equip you to embrace memory design. (More on this subject will be covered in a Webinar hosted on September 13th. See link below).


Links

September 13th Live Webinar: PathWave ADS 2023 for High-Speed Digital Design and Simulation (keysight.com) [ Ссылка ]

White Paper: The Road to DDR5
[ Ссылка ]

Application Note: Designing Leading-Edge Memory Systems
[ Ссылка ]

PCB Guidelines for Memory Interfaces • UltraScale Architecture PCB Design User Guide (UG583) •
[ Ссылка ]

UG583 Reader • Documentation Portal (xilinx.com)
[ Ссылка ]

More Resource Links:

Visit The EEcosystem Website  For a Free Download to: 100+ PCB Design Guidelines to Minimize Signal Integrity Problems by Eric Bogatin and receive a free 90-day subscription to all of Eric’s training at The Signal Integrity Academy

For SI/PI/EMI News and Technical Resources and to register for a free subscription visit the Signal Integrity Journal today.

For free Technical Resources and to Learn more about Keysight Pathwave EDA Software Solutions visit the homepage now.

For Custom RF and MW PCBs visit the Transline Technology Website to learn more.

Visit Summit Interconnect for all your PCB manufacturing needs.

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