This demo shows the output video of a learning-based Multiple Scale Pedestrian Detector implemented in Xilinx FPGA working with a wide angle rear-view camera. The green boxes represent the extracted pedestrians while the numbers in correspondence of the boxes are the degrees of confidence. This video shows only the result of the detection stage. The performance can be improved even further through the use of tracking algorithms.
This DA aid helps the driver during the parking manoeuvre by generating a warning in case a pedestrian is walking in the camera filed of view. The IP core PDET (Pedestrian DETector) is the fundamental functional block of the FPGA design. It is based on a HOG descriptor and a SVM classifier. It has been developed by eVS embedded Vision System Srl (www.embeddedvisionsystems.it).

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