The on-going explosion in low-power, short-range wireless communications has required a new style of RFIC design. Maintaining functionality while cutting power below 1mW requires a revision of everything from system level decisions down to basic circuit design choices. This lecture will briefly cover high-level system trade-offs, and their implications for SOC and subcircuit design: peer-to-peer topologies such as sensor networks have very different constraints from asymmetric topologies similar to RFID. This in turn drives system decisions like modulation type and duty-cycling, which must then be co-designed with critical circuits. Since power is limited by blocks such as RF oscillators, amplifiers, modulators and demodulators, optimization is required to reduce power in these circuits, and even to eliminate them when possible. This lecture will provide an overview of some popular system and architecture approaches and the circuit techniques that enable them.
