Digital Design and Computer Architecture, ETH Zürich, Spring 2020 ([ Ссылка ])
Discussion Session II
Lecturer: Professor Onur Mutlu ([ Ссылка ])
Date: June 13, 2020
Branch Prediction III (HW5, Q5): 00:08 - 14:56
Systolic Arrays I (HW5, Q8): 14:57 - 24:27
Vector Processing III (HW6, Q3): 24:28 - 41:59
GPUs and SIMD I (HW6, Q5): 42:00 - 50:41
GPUs and SIMD III (HW6, Q7): 50:42 - 01:10:08
GPUs and SIMD IV (HW6, Q8): 01:10:09 - 01:24:29
Reverse Engineering Caches II (HW7, Q3): 01:24:30 - 01:46:23
Tracing the Cache (HW7, Q4): 01:46:24 - 02:08:25
Cache Performance Analysis (HW7, Q7): 02:08:26 - 02:28:27
Memory Hierarchy (HW7, Q8): 02:28:28 - 02:45:19
Slides (pptx): [ Ссылка ]
Slides (pdf): [ Ссылка ]
