2024 LLVM Developers' Meeting
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New llvm-exegesis Support for RISC-V Vector Extension
Speaker: Min Hsu
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Slides: [ Ссылка ]
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llvm-exegesis has been instrumental in calibrating LLVM's scheduling models using hardware-collected metrics, such as instruction latency. In this talk, we'll unveil the first-ever llvm-exegesis support for RISC-V vector (RVV) instructions. We'll explore the challenges of scaling llvm-exegesis to accommodate the extensive range of RVV opcodes and configurations, and how we've significantly enhanced its efficiency for use in pre-silicon hardware development environments like FPGA. Our work not only advances RISC-V but also benefits the broader LLVM community by improving the quality of scheduling models with llvm-exegesis.
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Videos Edited by Bash Films: [ Ссылка ]

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