ROM Application in Pulse-Train Generators ROM is frequently used to build complex digital pulse train generators. Such devices are widely used in all kinds of measurement systems, automatics, television sets and control circuits for linear and matrix indicators. The most popular structure of ROM-based pulse train generators includes a clock generator of the required frequency, a counter with the required number of digits, ROM and an output register. The counter selects the ROM addresses, and the ROM produces in series all the codes recorded into it on the data outputs. The output register that is clocked by the same pulse clock as the counter is designed to prevent occurrence of parasitic pulses in output signals and to provide simultaneous switching of all the output signals (which is especially important in cases, when several ROM chips are connected in parallel to increase the bitness of the data bus). Let's say we need to uninterruptedly generate the set periodic sequence of 6 output signals in accordance with the time diagram. We can get this sequence using combination circuits that are connected to the counter output. Or we can use many single-shot multivibrators that actuate each other. But both the options will take up a lot of space and will be very difficult to implement in design and setup. Now, if we use ROM, the task will get much simpler. All we need to do is make a couple of simple calculations and develop a ROM weaving map. When conducting the calculations, we need to determine the minimum possible clock rate (in order to minimize the required ROM volume). To do that, let's identify the maximum time interval (time increment) that can fit into all the time shifts, delays and durations of the required diagram for an integer number of times. Now we need to determine the number of cells and the ROM bitness, which will depend upon the number of output signals. And finally, let's test the conditions of the circuit's correct operation. The train generator will operate correctly, if both, the counter and the ROM will be actuated within the clock signal period. This means that the sum of the delay in full switching of the counter and of the delay in ROM address selection should not exceed the clock signal period.
