The lesson covers Cell-Averaging Constant False Alarm Rate (CACFAR) implementation by using Vitis High Level Synthesis with mathematical modelling in Python and verification with Arty Z7-20 FPGA SoC

0:00 - Intro
1:24 - Cell-Averaging CFAR theory and HLS IP core microarchitecture
5:51 - HLS IP core performance
13:20 - HLS IP core co-simulation and real target debugging
17:10 - HLS IP core repository project

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