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Modular Designs: Components, Generate and Loops in VHDL - Hardware Description Languages for FPGA Design
FPGA Design for Embedded Systems Specialization
This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.
Writing Code in Verilog, Simulating FPGA Designs, Designing FPGA Logic, Designing Test Benches, Writing code in VHDL
I think this is a good start in learning how to write VHDL and Verilog. I would like to see a next level course or recommendations for further writing code.,The course helped in showing the different styles of the Verilog and VHDL coding. Understood the advantages of Verilog and VHDL in real life applications
In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.
Modular Designs: Components, Generate and Loops in VHDL - Hardware Description Languages for FPGA Design
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