In this video tutorial our circuit is a full adder, realized with the Verilog hardware description language. First we will test it with Verilog circuit simulation in TINACloud. Next, we will export the Verilog to the Quartus Prime Lite software, compile it and load the resulting bitstream into the Terasic DE10-Lite FPGA development board. Finally we will present how our simulated full adder circuit works along with the programmed Terasic DE10-Lite hardware and show that in all cases, the results are exactly the same.
