It's time to start HDL Development of PUF. In this video you learn how to:
1. Create Vivado project
2. Add source files
3. Write behavioral description of multiplexer on VHDL and Verilog
4. Elaborate design
5. Running design synthesis
6. Review of post-synthesis results
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The main blocks of Arbiter PUF are:
--MUX-pair based delay line
--D-flip-flop with input and clock connected to out of delay line
To Do:
--Create multiplexer (MUX)
--Build MUX-based delay line
--Describe D-flip-flop
--Combine all to Arbiter PUF
#fpga #pub #fpgabeginner
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2. contact me directly admin@fpgacommunity.com
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