This is the third in a series of videos about latches and flip-flops. These bi-stable combinations of logic gates form the basis of computer memory, counters, shift registers, and more. In particular, this video covers the gated D latch, otherwise known as the data latch or simply the D latch. It begins by reviewing the gated SR latch, including the risk of making both inputs high at the same time which results in a race condition and therefore an unpredictable state. It then shows how this problem can be overcome by a gated D latch. Two ways of building a gated D latch are covered and its behaviour is illustrated with a timing diagram. The videos that follow this one build upon the principles covered here and include the clocked D latch, edge triggered pulse latches and the master slave D type flip flop.

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